1. Field of the Invention
The present invention relates to an image processing apparatus and a control method for the same.
2. Description of the Related Art
Reconfigurable circuits such as a PLD (Programmable Logic Device) and an FPGA (Field Programmable Gate Array) that have changeable logic circuitry are well-known. Generally, when a PLD or an FPGA starts up, circuit configuration information stored in a non-volatile memory such as a ROM is written to a configuration memory, which is an internal volatile memory, and thus the logic circuitry is switched. Also, the information in the configuration memory is deleted when the power supply is interrupted, and therefore when power is supplied, it is necessary to reconfigure the logic circuitry by again writing the circuit configuration information from the non-volatile memory to the configuration memory. The method of configuring the logic circuitry of a PLD or an FPGA only one time in this way is called static reconfiguring.
On the other hand, FPGAs and the like whose logic circuitry can be changed while the circuitry is operating have been developed, and the method of changing the logic circuitry during operation is called dynamic reconfiguring. Also, there are FPGAs in which it is possible to rewrite simply a specific region instead of the entire chip, and this type of rewriting is called partial reconfiguring. In particular, there is a method of partially reconfiguring one logic circuitry portion without stopping the operation of other logic circuitry that is operating, and this method is called dynamic partial reconfiguring.
With dynamic partial reconfiguring, rather than rewriting the entirety of the configuration memory during dynamic reconfiguring, only a portion of the configuration memory region is rewritten, thus making it possible to partially reconfigure the logic circuitry in the FPGA. Using this dynamic partial reconfiguring technique enables implementing multiple logic circuits in one region of the FPGA, thus making it possible to realize a logic circuitry in which hardware resources are time-division multiplexed. As a result, various functions corresponding to various applications can be flexibly realized with few hardware resources, while maintaining high hardware operation performance.
As one example of a technique employing this dynamic partial reconfiguring, Japanese Patent Laid-Open No. 2011-186981 discloses a technique in which, in pipeline processing, data processing is performed while switching functions by performing reconfiguring in a reconfigurable circuit in order beginning with the circuit at the head of the pipeline.
In image processing apparatuses such as MFPs (Multi Function Printers) of recent years, it has been possible to select multiple processes (a copy job, a print job, a send job, and the like) corresponding to a request from a user, and image processing corresponding to the processes is executed by hardware or software. If a reconfigurable circuit such as an FPGA is employed as hardware for image processing in this image processing apparatus, the circuit configuration of the FPGA can be dynamically and partially switched in order to realize each of the various functions described above. As a result, various image processing functions can be realized with few hardware resources. Note that in a configuration for performing partial reconfiguring, if the partial reconfiguring fails for any of various reasons, such as a device failure, electrical noise, or a writing timing problem, it is not possible to configure the circuit that is needed, and it is not possible to realize intended data processing.
In the case of a reconfigurable circuit that is partially reconfigured during use as described above, if the partial reconfiguring fails, the performance of the apparatus degrades. For example, if some sort of reason causes the failure of partial reconfiguring for a certain image processing function needed for a specific image processing function, it will not be possible to use that image processing function, processing will stop, and the performance of the image processing apparatus will degrade. For this reason, with a configuration in which a reconfigurable circuit is partially reconfigured during use, it is necessary to implement the configuration with consideration given to the possibility of the failure of the partial reconfiguring.